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ZY1015 15A No-Bus POL Data Sheet
3V to 14V Input ? 0.5V to 5.5V Output
8.
8.1
Pin and Feature Description
VLDO, Low Voltage Dropout
fault occurs. Pulling low the OK input by an external
circuitry turns off the POL converter.
8.10 SYNC, Frequency Synchronization Line
The input of the internal linear regulator. V VLDO
always needs to be greater than 4.75V for normal
operation of the POL converter.
8.2 IM, Interleave Mode
The input with the internal pull-up resistor. When the
pin is left floating, the phase lag of the POL converter
is set by INTL0…INTL4 pins. If the pin is pulled low,
the phase lag is set to 0°. Pulling all INTL pins and
the IM pin low configures a POL converter as a
master. The master determines the clock on the
SYNC line.
The bidirectional input/output with the internal pull-up
resistor. If the POL converter is configured as a
master, the SYNC line propagates clock to other
POL converters. If the POL converter is configured
as a slave, the internal clock recovery circuit
synchronizes the POL converter to the clock of the
SYNC line.
8.11 PG, Power Good
The open drain input/output with the internal pull-up
resistor. The pin is pulled low by the POL converter,
if the output voltage is outside of the window defined
8.3
TEMP, Temperature Measurement
by the Power Good High and Low thresholds.
The voltage output of the internal temperature
sensor measuring junction temperature of the
controller IC. Voltage range from 0 to 2V
corresponds to the temperature range from -50°C to
150°C.
Note : See the No-Bus Application Note for recommendations on
PG deglitching.
8.12 TRIM, Output Voltage Trim
The input of the TRIM comparator for the output
8.4
ENP, Enable Polarity
voltage programming.
The input with the internal pull-up resistor. When the
ENP pin is pulled low, the control logic of the EN
input is inverted.
The output voltage can be programmed by a single
resistor connected between VREF and TRIM pins.
Resistance of the trim resistor can be determined
8.5
DELAY, Power-Up Delay
from the equation below:
The input of the POR circuit with the internal pull-up
resistor. By connecting a capacitor between the pin
and PGND the power-up delay can be programmed.
R TRIM ?
20 ? ( 5 . 5 ? V OUT )
V OUT
, k ?
8.6
CCA[0:2], Compensation Coefficient
Address
where V OUT is the desired output voltage in Volts.
Inputs with internal pull-ups to select one of 7 sets of
digital filter coefficients optimized for various
application conditions.
8.7 VREF, Voltage Reference
The output of the 2V internal voltage reference that
is used to program the output voltage of the POL
converter.
If the R TRIM is open or the TRIM pin is shorted to
PGND, the V OUT =0.5V.
8.13 CS, Current Share/Sense Bus
The open drain digital input/output with the internal
pull-up resistor. The duty cycle of the digital signal is
proportional to the output current of the POL
converter. External capacitive loading of the pin
8.8
EN, Enable
shall be avoided.
The input with the internal pull-up resistor. The POL
converter is turned off, when the pin is pulled low
(see ENP to inverse logic of the Enable function).
8.14 INTL[0:4], Interleave Bits
Inputs with internal pull-up resistors. The encoded
address determines the phase lag of the POL
8.9
OK, Fault Status
converter when the IM pin is left floating. One digit
The open drain input/output with the internal pull-up
resistor. The POL converter pulls its OK pin low, if a
of the address corresponds to the phase lag of
11.25°.
ZD-00993 Rev. 1.6, 24-Jun-10
www.power-one.com
Page 14 of 17
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